Field of the Invention: The present invention relates generally to computer memory devices and, more specifically, to capacitor cell containers formed in such semiconductor memory devices.
State of the Art: Computer memory devices, such as DRAM (dynamic random access memory) semiconductor device modules, utilize a series or an array of capacitors to store charge in retaining digital data for subsequent recall. Each capacitor is coupled to a transistor and includes a cell which holds a charge representative of a bit of data (i.e., a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d) depending on the charge of the cell. An array of capacitors, with a plurality of them holding a charge, allows for digital information to be stored in a compact and efficient manner which may be recalled by examining the charge on each capacitor. However, DRAM type memory requires constant refreshing at a rapid rate due to leakage from the capacitors. Thus, one of the inherent inefficiencies of DRAM type semiconductor device memory is the time and power utilized in the continual refreshing of the array of capacitors.
With the rapid advance in computer technology, DRAM semiconductor device memory modules have been designed with a higher density of memory cells. While such density of memory cells has led to expanded capacity in a smaller package, it has also produced new design challenges. For example, regardless of how small or how dense a storage cell array is packaged, each cell must hold a minimum amount of charge. Thus, in a high-density memory cell array, the ability to retain the minimum level of charge in a smaller volume memory needs to be addressed. One method of addressing such an issue has been to increase the effective surface area of the memory cell, and thus the electrode associated with the memory cell.
An example of increasing the surface area of a capacitor memory cell container may be seen in drawing FIG. 1, which shows a prior art partially fabricated memory cell within an integrated circuit such as a DRAM semiconductor memory device or chip. A conductive plug 10 located between neighboring word lines 12, usually comprising polysilicon, forms electrical contact with an active area 14 of a semiconductor substrate 16. A planarized insulating layer 18, such as borophosphosilicate glass (BPSG), surrounds the word lines 12. The conductive plug 10 is formed within an opening through the insulating layer 18. A structural layer 20 overlies the insulating layer 18 and may also be composed of BPSG or similar material. A container 22 is formed in the structural layer, generally by anisotropically etching the structural layer 20 through a mask. The container 22 is generally a cylindrical cavity formed contiguous with the conductive plug 10 and includes sidewalls 24 which extend to an opening in the structural layer 20. A layer 26 of hemispherical grained (HSG) polysilicon covers the interior surface of the container 22. The HSG layer 26 increases the surface area of the cell container 22 due to the hemispherical arrangement and patterning of the silicon. By increasing the surface area of the memory cell container, and thus an associated electrode, capacitance charge may be increased for a generally smaller cell container.
A thin layer of nitride 28 is deposited over the HSG layer 26 as well as the surface of the structural layer 20. It is noted that the nitride layer 28 grows much thinner over the surface of the BPSG structural layer 20 than on the HSG layer 26 due to the large nucleation incubation time of silicon nitride on BPSG. The slower growth of cell nitride on the BPSG layer 20 results in various problems. One problem is that the thin layer of nitride 28 on the structural layer 20 fails to effectively block oxygen during processes such as oxidation or followed oxidation (reox). The inefficiency of the thin cell nitride layer 28 allows oxygen to pass through the structural layer 20, resulting in the oxidation of the HSG layer 26. Of course, the amount of oxidation depends on the actual thickness of the nitride layer 28 above the structural layer 20. Additionally, the thin nitride layer 28 allows for current leakage at the edge of the container 22, thus creating an additional inefficiency with regard to the operation of the capacitor cell structure.
In view of the shortcomings in the art, it would be advantageous to provide a memory cell structure and a method for forming such a structure that assists in preventing oxidation of the cell plate. Further, it would be advantageous to provide a structure which is simple to manufacture and a method which does not significantly interfere with existing manufacturing processes. It would also be advantageous to provide a memory cell structure and method for manufacturing the structure with reduced current leakage at the edge of the cell container, thus improving the overall efficiency of the memory cell.
In accordance with one aspect of the invention, a method of forming a cell container for the capacitor of a memory device, such as a DRAM semiconductor memory device or chip or module, is provided. The method includes forming a structural layer above a conductive plug. A cavity is formed in the structural layer, such as by etching. The cavity includes at least one sidewall, such as a continual sidewall in a cylinder, a bottom surface which is contiguous with the conductive plug, and an opening at the upper surface of the structural layer. A layer of polysilicon is deposited over the bottom and sidewall of the cavity. A dielectric, such as a nitride layer, is formed over the polysilicon layer and at least a portion of the upper surface of the structural layer including the area surrounding the opening of the cavity at the opening thereof. A barrier layer is deposited over at least a portion of the dielectric layer including the area surrounding the opening of the cavity and a portion of the sidewall adjacent the opening. The barrier layer is deposited such that the majority of the sidewall as well as the bottom surface are not covered with the barrier layer. The container may then be subjected to an oxidation process wherein the barrier layer is oxidized and acts as an oxygen barrier for the structural layer.
The structural layer may be formed of BPSG with the polysilicon layer being formed of a hemispherical grained polysilicon to improve the surface area of the cell container. The dielectric layer may be formed of silicon nitride. Aluminum is a suitable material for the barrier layer and may be deposited by sputtering the aluminum on to help keep the aluminum layer from substantially covering the interior cell surface. Other metallic materials are also suitable, such as tantalum, zirconium, hafnium, tungsten, titanium or aluminum nitride. The formation of the metallic layer provides an oxygen barrier for the cell structure during oxidation processes, as well as leakage protection for the cell at the opening edge.
In accordance with another aspect of the invention, a memory cell container is provided. The memory cell includes a cavity formed in a structural layer such as BPSG. The cavity is formed to have a bottom, which is contiguous with a conductive plug, and a sidewall extending from the bottom of the cavity to an opening at the upper surface of the structural layer. A polysilicon layer, such as HSG polysilicon, is deposited in the cavity on the bottom and along the sidewall. A nitride layer, such as silicon nitride, is formed over the polysilicon layer and at least a portion of the upper surface of the structural layer. A barrier layer, such as aluminum, covers at least a portion of the nitride above the structural layer and a small portion of the nitride along the sidewall of the cavity adjacent the opening. The barrier layer forms an oxygen barrier for the cell container and also protects against edge leakage during operation. As with the method, various materials may be utilized to form the cell container, including various materials cited for the barrier layer.
In accordance with another aspect of the invention, a memory device is provided which includes a substrate having an array of capacitors formed therein. At least one of the capacitors includes a cell container similar to that described above including the metallic layer formed as an oxygen barrier.